A configurable semiconductor device in which a semiconductor element, such as a transistor, is formed on a semiconductor substrate so as to allow a metal wiring layer to be arbitrarily disposed so as to connect various elements disposed on the semiconductor substrate is known. This type of configurable semiconductor device can be formed into a custom-made system on chip (SoC) by arrangement of wirings in the metal wiring layer. By this process, it is possible to shorten a design and development period of new SoC devices, and greatly reduce design and development cost.
A configurable semiconductor memory device which applies this configurable metal layer to a memory device has been proposed.
However, a configurable semiconductor memory device in the related art comprises a memory macro cell including a memory cell array, an address decoder, a read/write circuit and a control circuit, and as such access in byte units is a prerequisite for these devices. One byte is usually eight bits. However, a byte unit is often set to nine bits by adding a parity bit for error correction purposes. Therefore, the memory macro cell operates with nine bits as a byte unit in some cases.
However, operation does not have to be performed in a byte unit, and the byte unit is not limited to nine bits. For example, in order to provide a redundant circuit, at least one redundant bit is required to be available for this purpose, such that the access unit may have to be ten bits. When a memory macro cell having a nine bit width is prepared in advance in a configurable memory device design, and it is subsequently desired to use ten bits (to provide the redundant bit), the number of bits in one memory cell array of the configurable memory device design is insufficient, and consequently at least one extra memory cell array in the configurable memory device design would be required to be used to provide the redundant bit space. However, among the 18 bits, which would be the total number of bits in two memory cell arrays in these scenario, only ten bits are actually used, such that nearly a half of memory capacity is wasted.
When a memory macro cell of a ten bit width is prepared to take into account the possible requirement of a redundant bit in the configurable memory device, then in many circumstances when less than ten bits are required, the redundant circuit is not used. As such, additional one bit portion of the memory macro cell is not used, and utilization efficiency of the memory cell is reduced.